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stm32 /stm32u5 /STM32U5Gx /FDCAN1_RAM /FDCAN_TXBC

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Interpret as FDCAN_TXBC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TFQM)TFQM

Description

FDCAN Tx buffer configuration register

Fields

TFQM

Tx FIFO/Queue Mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32