stm32 /stm32u5 /STM32U5Gx /GFXTIM /GFXTIM_EVCR

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Interpret as GFXTIM_EVCR

31282724232019161512118743000000000000000000000000000000000000000000 (B_0x0)EV1EN0 (B_0x0)EV2EN0 (B_0x0)EV3EN0 (B_0x0)EV4EN

EV4EN=B_0x0, EV3EN=B_0x0, EV2EN=B_0x0, EV1EN=B_0x0

Description

GFXTIM events control register

Fields

EV1EN

event 1 enable This bit enables the complex event 1 generation.

0 (B_0x0): event 1 generation disabled

1 (B_0x1): event 1 generation enabled

EV2EN

event 2 enable This bit enables the complex event 2 generation.

0 (B_0x0): event 2 generation disabled

1 (B_0x1): event 2 generation enabled

EV3EN

event 3 enable This bit enables the complex event 3 generation.

0 (B_0x0): event 3 generation disabled

1 (B_0x1): event 3 generation enabled

EV4EN

event 4 enable This bit enables the complex event 4 generation.

0 (B_0x0): event 4 generation disabled

1 (B_0x1): event 4 generation enabled

Links

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