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stm32 /stm32u5 /STM32U5Gx /PSSI /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RTT4B)RTT4B 0 (RTT1B)RTT1B

Description

PSSI status register

Fields

RTT4B

RTT4B
RTT1B

RTT1B

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32