stm32 /stm32u5 /STM32U5Gx /PWR /PWR_BDCR1

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Interpret as PWR_BDCR1

31282724232019161512118743000000000000000000000000000000000000000000 (B_0x0)BREN0 (B_0x0)MONEN

BREN=B_0x0, MONEN=B_0x0

Description

PWR Backup domain control register 1

Fields

BREN

Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept in Standby and VBAT modes. If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS. Note: Backup RAM cannot be preserved in Shutdown mode.

0 (B_0x0): Backup RAM content lost in Standby and VBAT modes

1 (B_0x1): Backup RAM content preserved in Standby and VBAT modes

MONEN

Backup domain voltage and temperature monitoring enable

0 (B_0x0): Backup domain voltage and temperature monitoring disabled

1 (B_0x1): Backup domain voltage and temperature monitoring enabled

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