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stm32 /stm32u5 /STM32U5Gx /SDMMC1 /SDMMC_IDMACTRLR

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Interpret as SDMMC_IDMACTRLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IDMAEN)IDMAEN 0 (IDMABMODE)IDMABMODE

Description

DMA control register

Fields

IDMAEN

IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
IDMABMODE

Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32