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stm32 /stm32wb /STM32WB10_CM4 /LPTIM1 /ISR

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Interpret as ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CMPM)CMPM 0 (ARRM)ARRM 0 (EXTTRIG)EXTTRIG 0 (CMPOK)CMPOK 0 (ARROK)ARROK 0 (UP)UP 0 (DOWN)DOWN

Description

Interrupt and Status Register

Fields

CMPM

Compare match
ARRM

Autoreload match
EXTTRIG

External trigger edge event
CMPOK

Compare register update OK
ARROK

Autoreload register update OK
UP

Counter direction change down to up
DOWN

Counter direction change up to down

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32