stm32 /stm32wb /STM32WB10_CM4 /RCC /CICR

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Interpret as CICR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSI1RDYC)LSI1RDYC 0 (LSERDYC)LSERDYC 0 (MSIRDYC)MSIRDYC 0 (HSIRDYC)HSIRDYC 0 (HSERDYC)HSERDYC 0 (PLLRDYC)PLLRDYC 0 (PLLSAI1RDYC)PLLSAI1RDYC 0 (HSECSSC)HSECSSC 0 (LSECSSC)LSECSSC 0 (HSI48RDYC)HSI48RDYC 0 (LSI2RDYC)LSI2RDYC

Description

Clock interrupt clear register

Fields

LSI1RDYC

LSI1 ready interrupt clear

LSERDYC

LSE ready interrupt clear

MSIRDYC

MSI ready interrupt clear

HSIRDYC

HSI ready interrupt clear

HSERDYC

HSE ready interrupt clear

PLLRDYC

PLL ready interrupt clear

PLLSAI1RDYC

PLLSAI1 ready interrupt clear

HSECSSC

HSE Clock security system interrupt clear

LSECSSC

LSE Clock security system interrupt clear

HSI48RDYC

HSI48 ready interrupt clear

LSI2RDYC

LSI2 ready interrupt clear

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