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stm32 /stm32wb /STM32WB15_CM4 /DBGMCU /APB2FZR

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Interpret as APB2FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_TIM1_STOP)DBG_TIM1_STOP

Description

APB2 Freeze Register CPU1

Fields

DBG_TIM1_STOP

TIM1 counter stopped when core is halted

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32