Regviz

stm32 /stm32wb /STM32WB15_CM4 /IPCC /C1TO2SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as C1TO2SR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb/STM32WB10_CM4/IPCC/C1TO2SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH1F)CH1F 0 (CH2F)CH2F 0 (CH3F)CH3F 0 (CH4F)CH4F 0 (CH5F)CH5F 0 (CH6F)CH6F

Description

CPU1 to CPU2 status register

Fields

CH1F

processor 1 transmit to process 2 Receive channel 1 status flag
CH2F

processor 1 transmit to process 2 Receive channel 2 status flag
CH3F

processor 1 transmit to process 2 Receive channel 3 status flag
CH4F

processor 1 transmit to process 2 Receive channel 4 status flag
CH5F

processor 1 transmit to process 2 Receive channel 5 status flag
CH6F

processor 1 transmit to process 2 Receive channel 6 status flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32