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stm32 /stm32wb /STM32WB15_CM4 /RCC /APB1RSTR1

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Interpret as APB1RSTR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM2RST)TIM2RST 0 (LCDRST)LCDRST 0 (SPI2RST)SPI2RST 0 (I2C1RST)I2C1RST 0 (I2C3RST)I2C3RST 0 (CRSRST)CRSRST 0 (USBFSRST)USBFSRST 0 (LPTIM1RST)LPTIM1RST

Description

APB1 peripheral reset register 1

Fields

TIM2RST

TIM2 timer reset
LCDRST

LCD interface reset
SPI2RST

SPI2 reset
I2C1RST

I2C1 reset
I2C3RST

I2C3 reset
CRSRST

CRS reset
USBFSRST

USB FS reset
LPTIM1RST

Low Power Timer 1 reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32