C2AHB1SMENR

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Interpret as C2AHB1SMENR

CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register

DMA1SMEN	CPU2 DMA1 clocks enable during Sleep and Stop modes
DMA2SMEN	CPU2 DMA2 clocks enable during Sleep and Stop modes
DMAMUXSMEN	CPU2 DMAMUX clocks enable during Sleep and Stop modes
SRAM1SMEN	SRAM1 interface clock enable during CPU1 CSleep mode
CRCSMEN	CPU2 CRCSMEN
TSCSMEN	CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes

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