Regviz

stm32 /stm32wb /STM32WB15_CM4 /RCC /PLLSAI1CFGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PLLSAI1CFGR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb/STM32WB10_CM4/RCC/PLLSAI1CFGR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLLN0 (PLLPEN)PLLPEN 0PLLP0 (PLLQEN)PLLQEN 0PLLQ0 (PLLREN)PLLREN 0PLLR

Description

PLLSAI1 configuration register

Fields

PLLN

SAIPLL multiplication factor for VCO
PLLPEN

SAIPLL PLLSAI1CLK output enable
PLLP

SAI1PLL division factor P for PLLSAICLK (SAI1clock)
PLLQEN

SAIPLL PLLSAIUSBCLK output enable
PLLQ

SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
PLLREN

PLLSAI PLLADC1CLK output enable
PLLR

PLLSAI division factor R for PLLADC1CLK (ADC clock)

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32