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stm32 /stm32wb /STM32WB15_CM4 /TIM2 /OR

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Interpret as OR

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https://regviz.com/r/stm32/stm32wb/STM32WB10_CM4/TIM2/OR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ITR_RMP)ITR_RMP 0 (ETR_RMP)ETR_RMP 0TI4_RMP

Description

TIM2 option register

Fields

ITR_RMP

Internal trigger remap
ETR_RMP

External trigger remap
TI4_RMP

Input capture 4 remap

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32