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stm32 /stm32wb /STM32WB50_CM4 /GPIOE /IDR

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Interpret as IDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IDR0)IDR0 0 (IDR1)IDR1 0 (IDR2)IDR2 0 (IDR3)IDR3 0 (IDR4)IDR4

Description

GPIO port input data register

Fields

IDR0

Port input data (y = 0…15)
IDR1

Port input data (y = 0…15)
IDR2

Port input data (y = 0…15)
IDR3

Port input data (y = 0…15)
IDR4

Port input data (y = 0…15)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32