Regviz

stm32 /stm32wb /STM32WB50_CM4 /HSEM /RLR19

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RLR19

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb/STM32WB30_CM4/HSEM/RLR19#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PROCID0COREID0 (LOCK)LOCK

Description

Semaphore 19 read lock register

Fields

PROCID

Semaphore ProcessID
COREID

Semaphore CoreID
LOCK

lock indication

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32