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stm32 /stm32wb /STM32WB50_CM4 /IPCC /C1MR

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Interpret as C1MR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH1OM)CH1OM 0 (CH2OM)CH2OM 0 (CH3OM)CH3OM 0 (CH4OM)CH4OM 0 (CH5OM)CH5OM 0 (CH6OM)CH6OM 0 (CH1FM)CH1FM 0 (CH2FM)CH2FM 0 (CH3FM)CH3FM 0 (CH4FM)CH4FM 0 (CH5FM)CH5FM 0 (CH6FM)CH6FM

Description

Mask register CPU1

Fields

CH1OM

processor 1 Receive channel 1 occupied interrupt enable
CH2OM

processor 1 Receive channel 2 occupied interrupt enable
CH3OM

processor 1 Receive channel 3 occupied interrupt enable
CH4OM

processor 1 Receive channel 4 occupied interrupt enable
CH5OM

processor 1 Receive channel 5 occupied interrupt enable
CH6OM

processor 1 Receive channel 6 occupied interrupt enable
CH1FM

processor 1 Transmit channel 1 free interrupt mask
CH2FM

processor 1 Transmit channel 2 free interrupt mask
CH3FM

processor 1 Transmit channel 3 free interrupt mask
CH4FM

processor 1 Transmit channel 4 free interrupt mask
CH5FM

processor 1 Transmit channel 5 free interrupt mask
CH6FM

processor 1 Transmit channel 6 free interrupt mask

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32