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stm32 /stm32wb /STM32WB50_CM4 /IPCC /C2TOC1SR

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Interpret as C2TOC1SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH1F)CH1F 0 (CH2F)CH2F 0 (CH3F)CH3F 0 (CH4F)CH4F 0 (CH5F)CH5F 0 (CH6F)CH6F

Description

CPU2 to CPU1 status register

Fields

CH1F

processor 2 transmit to process 1 Receive channel 1 status flag
CH2F

processor 2 transmit to process 1 Receive channel 2 status flag
CH3F

processor 2 transmit to process 1 Receive channel 3 status flag
CH4F

processor 2 transmit to process 1 Receive channel 4 status flag
CH5F

processor 2 transmit to process 1 Receive channel 5 status flag
CH6F

processor 2 transmit to process 1 Receive channel 6 status flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32