stm32 /stm32wb /STM32WB50_CM4 /IPCC /HWCFGR

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Interpret as HWCFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CHANNELS

Description

IPCC Hardware configuration register

Fields

CHANNELS

Number of channels per CPU supported by the IP, range 1 to 16

Links

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