stm32 /stm32wb /STM32WB50_CM4 /PWR /CR3

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Interpret as CR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EWUP1)EWUP1 0 (EWUP2)EWUP2 0 (EWUP3)EWUP3 0 (EWUP4)EWUP4 0 (EWUP5)EWUP5 0 (EBORHSDFB)EBORHSDFB 0 (RRS)RRS 0 (APC)APC 0 (EBLEA)EBLEA 0 (ECRPE)ECRPE 0 (E802A)E802A 0 (EC2H)EC2H 0 (EIWUL)EIWUL

Description

Power control register 3

Fields

EWUP1

Enable Wakeup pin WKUP1

EWUP2

Enable Wakeup pin WKUP2

EWUP3

Enable Wakeup pin WKUP3

EWUP4

Enable Wakeup pin WKUP4

EWUP5

Enable Wakeup pin WKUP5

EBORHSDFB

Enable BORH and Step Down counverter forced in Bypass interrups for CPU1

RRS

SRAM2a retention in Standby mode

APC

Apply pull-up and pull-down configuration

EBLEA

Enable BLE end of activity interrupt for CPU1

ECRPE

Enable critical radio phase end of activity interrupt for CPU1

E802A

Enable end of activity interrupt for CPU1

EC2H

Enable CPU2 Hold interrupt for CPU1

EIWUL

Enable internal wakeup line for CPU1

Links

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