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stm32 /stm32wb /STM32WB50_CM4 /RCC /AHB1SMENR

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Interpret as AHB1SMENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA1SMEN)DMA1SMEN 0 (DMA2SMEN)DMA2SMEN 0 (DMAMUXSMEN)DMAMUXSMEN 0 (SRAM1SMEN)SRAM1SMEN 0 (CRCSMEN)CRCSMEN 0 (TSCSMEN)TSCSMEN

Description

AHB1 peripheral clocks enable in Sleep and Stop modes register

Fields

DMA1SMEN

CPU1 DMA1 clocks enable during Sleep and Stop modes
DMA2SMEN

CPU1 DMA2 clocks enable during Sleep and Stop modes
DMAMUXSMEN

CPU1 DMAMUX clocks enable during Sleep and Stop modes
SRAM1SMEN

CPU1 SRAM1 interface clocks enable during Sleep and Stop modes
CRCSMEN

CPU1 CRCSMEN
TSCSMEN

CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32