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stm32 /stm32wb /STM32WB50_CM4 /RCC /AHB2RSTR

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Interpret as AHB2RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GPIOARST)GPIOARST 0 (GPIOBRST)GPIOBRST 0 (GPIOCRST)GPIOCRST 0 (GPIODRST)GPIODRST 0 (GPIOERST)GPIOERST 0 (GPIOHRST)GPIOHRST 0 (ADCRST)ADCRST 0 (AES1RST)AES1RST

Description

AHB2 peripheral reset register

Fields

GPIOARST

IO port A reset
GPIOBRST

IO port B reset
GPIOCRST

IO port C reset
GPIODRST

IO port D reset
GPIOERST

IO port E reset
GPIOHRST

IO port H reset
ADCRST

ADC reset
AES1RST

AES1 hardware accelerator reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32