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stm32 /stm32wb /STM32WB50_CM4 /RCC /APB1ENR2

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Interpret as APB1ENR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPTIM2EN)LPTIM2EN

Description

APB1 peripheral clock enable register 2

Fields

LPTIM2EN

CPU1 LPTIM2EN

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32