Regviz

stm32 /stm32wb /STM32WB50_CM4 /RCC /APB1SMENR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as APB1SMENR2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb/STM32WB30_CM4/RCC/APB1SMENR2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPTIM2SMEN)LPTIM2SMEN

Description

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Fields

LPTIM2SMEN

Low power timer 2 clocks enable during CPU1 Sleep mode

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32