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stm32 /stm32wb /STM32WB50_CM4 /RCC /C2AHB3SMENR

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Interpret as C2AHB3SMENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PKASMEN)PKASMEN 0 (AES2SMEN)AES2SMEN 0 (RNGSMEN)RNGSMEN 0 (SRAM2SMEN)SRAM2SMEN 0 (FLASHSMEN)FLASHSMEN

Description

CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register

Fields

PKASMEN

PKA accelerator clocks enable during CPU2 sleep modes
AES2SMEN

AES2 accelerator clocks enable during CPU2 sleep modes
RNGSMEN

True RNG clocks enable during CPU2 sleep modes
SRAM2SMEN

SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes
FLASHSMEN

Flash interface clocks enable during CPU2 sleep modes

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32