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stm32 /stm32wb /STM32WB50_CM4 /RCC /C2APB1SMENR2

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Interpret as C2APB1SMENR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPTIM2SMEN)LPTIM2SMEN

Description

CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2

Fields

LPTIM2SMEN

Low power timer 2 clocks enable during CPU2 Sleep mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32