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stm32 /stm32wb /STM32WB50_CM4 /RCC /CRRCR

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Interpret as CRRCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HSI48ON)HSI48ON 0 (HSI48RDY)HSI48RDY 0HSI48CAL

Description

Clock recovery RC register

Fields

HSI48ON

HSI48 oscillator enabled
HSI48RDY

HSI48 clock ready
HSI48CAL

HSI48 clock calibration

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32