Regviz

stm32 /stm32wb /STM32WB50_CM4 /TIM17 /OR

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Interpret as OR

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https://regviz.com/r/stm32/stm32wb/STM32WB30_CM4/TIM16/OR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TI1_RMP

Description

TIM16 option register 1

Fields

TI1_RMP

Input capture 1 remap

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32