Regviz

stm32 /stm32wb /STM32WB55_CM0P /ADC /DR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DR

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https://regviz.com/r/stm32/stm32wb/STM32WB30_CM4/ADC/DR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDATA_0_60RDATA_7_15

Description

ADC group regular conversion data register

Fields

RDATA_0_6

Regular Data converted 0_6
RDATA_7_15

15

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32