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stm32 /stm32wb /STM32WB55_CM0P /CRS /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYNCOKIE)SYNCOKIE 0 (SYNCWARNIE)SYNCWARNIE 0 (ERRIE)ERRIE 0 (ESYNCIE)ESYNCIE 0 (CEN)CEN 0 (AUTOTRIMEN)AUTOTRIMEN 0 (SWSYNC)SWSYNC 0TRIM

Description

CRS control register

Fields

SYNCOKIE

SYNC event OK interrupt enable
SYNCWARNIE

SYNC warning interrupt enable
ERRIE

Synchronization or trimming error interrupt enable
ESYNCIE

Expected SYNC interrupt enable
CEN

Frequency error counter enable
AUTOTRIMEN

Automatic trimming enable
SWSYNC

Automatic trimming enable
TRIM

HSI48 oscillator smooth trimming

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32