Regviz

stm32 /stm32wb /STM32WB55_CM0P /CRS /ICR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ICR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb/STM32WB35_CM4/CRS/ICR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYNCOKC)SYNCOKC 0 (SYNCWARNC)SYNCWARNC 0 (ERRC)ERRC 0 (ESYNCC)ESYNCC

Description

CRS interrupt flag clear register

Fields

SYNCOKC

SYNC event OK clear flag
SYNCWARNC

warning clear flag
ERRC

Error clear flag
ESYNCC

Expected SYNC clear flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32