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stm32 /stm32wb /STM32WB55_CM0P /DBGMCU /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_SLEEP)DBG_SLEEP 0 (DBG_STOP)DBG_STOP 0 (DBG_STANDBY)DBG_STANDBY 0 (TRACE_IOEN)TRACE_IOEN 0 (TRGOEN)TRGOEN

Description

Debug MCU Configuration Register

Fields

DBG_SLEEP

Debug Sleep Mode
DBG_STOP

Debug Stop Mode
DBG_STANDBY

Debug Standby Mode
TRACE_IOEN

Trace port and clock enable
TRGOEN

External trigger output enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32