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stm32 /stm32wb /STM32WB55_CM0P /DMAMUX1 /C4CR

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Interpret as C4CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMAREQ_ID0 (SOIE)SOIE 0 (EGE)EGE 0 (SE)SE 0SPOL 0NBREQ0SYNC_ID

Description

DMA Multiplexer Channel 4 Control register

Fields

DMAREQ_ID

DMA Request ID
SOIE

Synchronization Overrun Interrupt Enable
EGE

Event Generation Enable
SE

Synchronization enable
SPOL

Sync polarity
NBREQ

Nb request
SYNC_ID

SYNC_ID

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32