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stm32 /stm32wb /STM32WB55_CM0P /DMAMUX1 /CFR

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Interpret as CFR

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https://regviz.com/r/stm32/stm32wb/STM32WB15_CM4/DMAMUX/CFR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CSOF0)CSOF0 0 (CSOF1)CSOF1 0 (CSOF2)CSOF2 0 (CSOF3)CSOF3 0 (CSOF4)CSOF4 0 (CSOF5)CSOF5 0 (CSOF6)CSOF6 0 (CSOF7)CSOF7 0 (CSOF8)CSOF8 0 (CSOF9)CSOF9 0 (CSOF10)CSOF10 0 (CSOF11)CSOF11 0 (CSOF12)CSOF12 0 (CSOF13)CSOF13

Description

DMA Channel Clear Flag Register

Fields

CSOF0

Synchronization Clear Overrun Flag 0
CSOF1

Synchronization Clear Overrun Flag 1
CSOF2

Synchronization Clear Overrun Flag 2
CSOF3

Synchronization Clear Overrun Flag 3
CSOF4

Synchronization Clear Overrun Flag 4
CSOF5

Synchronization Clear Overrun Flag 5
CSOF6

Synchronization Clear Overrun Flag 6
CSOF7

Synchronization Clear Overrun Flag 7
CSOF8

Synchronization Clear Overrun Flag 8
CSOF9

Synchronization Clear Overrun Flag 9
CSOF10

Synchronization Clear Overrun Flag 10
CSOF11

Synchronization Clear Overrun Flag 11
CSOF12

Synchronization Clear Overrun Flag 12
CSOF13

Synchronization Clear Overrun Flag 13

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32