Regviz

stm32 /stm32wb /STM32WB55_CM0P /DMAMUX1 /CSR

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Interpret as CSR

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https://regviz.com/r/stm32/stm32wb/STM32WB30_CM4/DMAMUX/CSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SOF0)SOF0 0 (SOF1)SOF1 0 (SOF2)SOF2 0 (SOF3)SOF3 0 (SOF4)SOF4 0 (SOF5)SOF5 0 (SOF6)SOF6 0 (SOF7)SOF7 0 (SOF8)SOF8 0 (SOF9)SOF9 0 (SOF10)SOF10 0 (SOF11)SOF11 0 (SOF12)SOF12 0 (SOF13)SOF13

Description

DMA Multiplexer Channel Status register

Fields

SOF0

Synchronization Overrun Flag 0
SOF1

Synchronization Overrun Flag 1
SOF2

Synchronization Overrun Flag 2
SOF3

Synchronization Overrun Flag 3
SOF4

Synchronization Overrun Flag 4
SOF5

Synchronization Overrun Flag 5
SOF6

Synchronization Overrun Flag 6
SOF7

Synchronization Overrun Flag 7
SOF8

Synchronization Overrun Flag 8
SOF9

Synchronization Overrun Flag 9
SOF10

Synchronization Overrun Flag 10
SOF11

Synchronization Overrun Flag 11
SOF12

Synchronization Overrun Flag 12
SOF13

Synchronization Overrun Flag 13

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32