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stm32 /stm32wb /STM32WB55_CM0P /EXTI /HWCFGR5

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Interpret as HWCFGR5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CPUEVENT

Description

Hardware configuration registers

Fields

CPUEVENT

HW configuration CPU event generation

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32