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stm32 /stm32wb /STM32WB55_CM0P /Flash /ACR

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Interpret as ACR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LATENCY 0 (PRFTEN)PRFTEN 0 (ICEN)ICEN 0 (DCEN)DCEN 0 (ICRST)ICRST 0 (DCRST)DCRST 0 (PES)PES 0 (EMPTY)EMPTY

Description

Access control register

Fields

LATENCY

Latency
PRFTEN

Prefetch enable
ICEN

Instruction cache enable
DCEN

Data cache enable
ICRST

Instruction cache reset
DCRST

Data cache reset
PES

CPU1 CortexM4 program erase suspend request
EMPTY

Flash User area empty

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32