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stm32 /stm32wb /STM32WB55_CM0P /GPIOE /OSPEEDR

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Interpret as OSPEEDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0OSPEEDR0 0OSPEEDR1 0OSPEEDR2 0OSPEEDR3 0OSPEEDR4

Description

GPIO port output speed register

Fields

OSPEEDR0

Port x configuration bits (y = 0…15)
OSPEEDR1

Port x configuration bits (y = 0…15)
OSPEEDR2

Port x configuration bits (y = 0…15)
OSPEEDR3

Port x configuration bits (y = 0…15)
OSPEEDR4

Port x configuration bits (y = 0…15)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32