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stm32 /stm32wb /STM32WB55_CM0P /GPIOH /BRR

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Interpret as BRR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BR0)BR0 0 (BR1)BR1 0 (BR3)BR3

Description

port bit reset register

Fields

BR0

Port Reset bit
BR1

Port Reset bit
BR3

Port Reset bit

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32