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stm32 /stm32wb /STM32WB55_CM0P /GPIOH /BSRR

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Interpret as BSRR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BS0)BS0 0 (BS1)BS1 0 (BS3)BS3 0 (BR0)BR0 0 (BR1)BR1 0 (BR3)BR3

Description

GPIO port bit set/reset register

Fields

BS0

Port x set bit y (y= 0…15)
BS1

Port x set bit y (y= 0…15)
BS3

Port x set bit y (y= 0…15)
BR0

Port x set bit y (y= 0…15)
BR1

Port x reset bit y (y = 0…15)
BR3

Port x reset bit y (y = 0…15)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32