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stm32 /stm32wb /STM32WB55_CM0P /GPIOH /LCKR

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Interpret as LCKR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LCK0)LCK0 0 (LCK1)LCK1 0 (LCK3)LCK3 0 (LCKK)LCKK

Description

GPIO port configuration lock register

Fields

LCK0

Port x lock bit y (y= 0…15)
LCK1

Port x lock bit y (y= 0…15)
LCK3

Port x lock bit y (y= 0…15)
LCKK

Port x lock bit y (y= 0…15)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32