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stm32 /stm32wb /STM32WB55_CM0P /GPIOH /ODR

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Interpret as ODR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ODR0)ODR0 0 (ODR1)ODR1 0 (ODR3)ODR3

Description

GPIO port output data register

Fields

ODR0

Port output data (y = 0…15)
ODR1

Port output data (y = 0…15)
ODR3

Port output data (y = 0…15)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32