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stm32 /stm32wb /STM32WB55_CM0P /HSEM /C1IER0

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Interpret as C1IER0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ISEm

Description

HSEM Interrupt enable register

Fields

ISEm

CPU(n) semaphore m enable bit

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32