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stm32 /stm32wb /STM32WB55_CM0P /IPCC /C1CR

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Interpret as C1CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXOIE)RXOIE 0 (TXFIE)TXFIE

Description

Control register CPU1

Fields

RXOIE

processor 1 Receive channel occupied interrupt enable
TXFIE

processor 1 Transmit channel free interrupt enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32