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stm32 /stm32wb /STM32WB55_CM0P /IPCC /C2SCR

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Interpret as C2SCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH1C)CH1C 0 (CH2C)CH2C 0 (CH3C)CH3C 0 (CH4C)CH4C 0 (CH5C)CH5C 0 (CH6C)CH6C 0 (CH1S)CH1S 0 (CH2S)CH2S 0 (CH3S)CH3S 0 (CH4S)CH4S 0 (CH5S)CH5S 0 (CH6S)CH6S

Description

Status Set or Clear register CPU2

Fields

CH1C

processor 2 Receive channel 1 status clear
CH2C

processor 2 Receive channel 2 status clear
CH3C

processor 2 Receive channel 3 status clear
CH4C

processor 2 Receive channel 4 status clear
CH5C

processor 2 Receive channel 5 status clear
CH6C

processor 2 Receive channel 6 status clear
CH1S

processor 2 Transmit channel 1 status set
CH2S

processor 2 Transmit channel 2 status set
CH3S

processor 2 Transmit channel 3 status set
CH4S

processor 2 Transmit channel 4 status set
CH5S

processor 2 Transmit channel 5 status set
CH6S

processor 2 Transmit channel 6 status set

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32