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stm32 /stm32wb /STM32WB55_CM0P /LCD /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENS)ENS 0 (SOF)SOF 0 (UDR)UDR 0 (UDD)UDD 0 (RDY)RDY 0 (FCRSF)FCRSF

Description

status register

Fields

ENS

ENS
SOF

Start of frame flag
UDR

Update display request
UDD

Update Display Done
RDY

Ready flag
FCRSF

LCD Frame Control Register Synchronization flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32