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stm32 /stm32wb /STM32WB55_CM0P /LPTIM1 /OR

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Interpret as OR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OR1)OR1 0 (OR2)OR2

Description

Option Register

Fields

OR1

Option register bit 1
OR2

Option register bit 2

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32