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stm32 /stm32wb /STM32WB55_CM0P /PWR /CR1

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Interpret as CR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LPMS0 (FPDR)FPDR 0 (FPDS)FPDS 0 (DBP)DBP 0VOS0 (LPR)LPR

Description

Power control register 1

Fields

LPMS

Low-power mode selection for CPU1
FPDR

Flash power down mode during LPRun for CPU1
FPDS

Flash power down mode during LPsSleep for CPU1
DBP

Disable backup domain write protection
VOS

Voltage scaling range selection
LPR

Low-power run

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32