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stm32 /stm32wb /STM32WB55_CM0P /PWR /EXTSCR

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Interpret as EXTSCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (C1CSSF)C1CSSF 0 (C2CSSF)C2CSSF 0 (CCRPF)CCRPF 0 (C1SBF)C1SBF 0 (C1STOPF)C1STOPF 0 (C2SBF)C2SBF 0 (C2STOPF)C2STOPF 0 (CRPF)CRPF 0 (C1DS)C1DS 0 (C2DS)C2DS

Description

Power status clear register

Fields

C1CSSF

Clear CPU1 Stop Standby flags
C2CSSF

Clear CPU2 Stop Standby flags
CCRPF

Clear Critical Radio system phase
C1SBF

System Standby flag for CPU1
C1STOPF

System Stop flag for CPU1
C2SBF

System Standby flag for CPU2
C2STOPF

System Stop flag for CPU2
CRPF

Critical Radio system phase
C1DS

CPU1 deepsleep mode
C2DS

CPU2 deepsleep mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32