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stm32 /stm32wb /STM32WB55_CM0P /QUADSPI /CCR

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Interpret as CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INSTRUCTION0IMODE 0ADMODE 0ADSIZE 0ABMODE 0ABSIZE 0DCYC0DMODE 0FMODE 0 (SIOO)SIOO 0 (DDRM)DDRM

Description

communication configuration register

Fields

INSTRUCTION

Instruction
IMODE

Instruction mode
ADMODE

Address mode
ADSIZE

Address size
ABMODE

Alternate bytes mode
ABSIZE

Alternate bytes size
DCYC

Number of dummy cycles
DMODE

Data mode
FMODE

Functional mode
SIOO

Send instruction only once mode
DDRM

Double data rate mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32