Regviz

stm32 /stm32wb /STM32WB55_CM0P /QUADSPI /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TEF)TEF 0 (TCF)TCF 0 (FTF)FTF 0 (SMF)SMF 0 (TOF)TOF 0 (BUSY)BUSY 0FLEVEL

Description

status register

Fields

TEF

Transfer error flag
TCF

Transfer complete flag
FTF

FIFO threshold flag
SMF

Status match flag
TOF

Timeout flag
BUSY

Busy
FLEVEL

FIFO level

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32